This invention relates to data acquisition and test & measurement circuitry such as digital-to-analog conversion (DAC) and analog-to-digital (ADC) circuits, and more particularly, relates to a latching CMOS comparator circuit, especially useful in sampled ADC applications.
Since A/D conversion techniques generally require combining analog and digital signal processing in the same chip, they are well suited for monolithic implementation in a MOS technology, such as CMOS technology. A number of circuit approaches have been developed for designing converters with MOS devices.
Successive-approximation converters represent an excellent compromise or trade-off between physical circuit size and converter speed requirements. The voltage comparator is a key element in the design of such devices. It is desirable that the comparator design be simple, tolerant to operating environment variations, and especially tolerant of mismatches in integrated circuit fabrication.
For data acquisition applications, among others, a comparator must also have latching capability. In other words, subsequent to a latch command, or latch clock signal transition (e.g. in a successive approximation ADC), the input stage of the comparator would be disabled and the logic state at the output stored indefinitely, until an enable or unlatched command (or subsequent latch clock state change) occurs. The changing voltage of the latch clock signal, however, can inject current into the comparator, via the parasitic gate capacitance, at latch time. This latching current surge can result in undesirable voltage offset due to device mismatch.